1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly, to a dual gate oxide process.
2. Description of Related Art
The electrostatic discharge (ESD) has been one of the major causes that damage an integrated circuit in a semiconductor fabrication process. In a deep sub-micron integrated circuit, the ESD even more seriously causes the malfunction of an integrated circuit or even damages the circuit. In order to overcome the problems caused by the ESD, an on-chip ESD protection circuit is added to the pads at the output end and the input end of a complement metal-oxide-semiconductor (CMOS). However, according to the process on the semiconductor fabrication process, the protection of the ESD protection circuit is no longer meets the practical needs.
A conventional ESD protection circuit including a field device transistor is shown in FIG. 1. Referring to FIG. 1, static voltage or over-stress voltage at the input port I/P is discharged through a N-type field device transistor 10 to the ground V.sub.SS. The input buffer gate 12 and the internal circuit 14 are under the protection of the field device transistor 10.
The cross sectional view of the N-type field device transistor 10 in FIG. 1 is shown in FIG. 2. Referring to FIG. 2, a conventional N-type field device transistor includes a gate 25, a source region 22 and a drain region 23 formed on a substrate 20. There further is a field oxide layer 24 located between the source region 22 and the drain region 23. For an N-type field device transistor, a heavy doped P-type region 26 is formed under the field oxide layer 24. The source region 22 is grounded by connected to a ground V.sub.SS through an interconnect 27. In the mean time, the gate 27 and the drain region 23 are connected to the input port I/P and the buffer input gate 12 shown in FIG. 1 through the interconnect 27. The foregoing connection is capable of protecting the internal circuit 14 from an over-stress voltage due to ESD by bypass the over-stress voltage.
In the case than an over-stress voltage appears at the input port I/P, the field device 10 bypasses the over-stress voltage signal by applying the principle of punch-through effect. Theoretically, the punch-through effect of the field device transistor 10 has a faster response to an over-stress voltage before the over-stress voltage causes a junction breakdown on the field effect transistor 10. Hence, the field device transistor 10 can be used as a protection to prevent the breakdown occurs on the low-voltage gate oxide layers in the internal circuit.
Conventionally, a heavy P-type implantation process is used to improve the isolation between devices that also forms a P-type heavy doped region 26 underneath the field oxide 24 of the field device transistor 10. In the presence of the P-type heavy doped region 26, the threshold voltage V.sub.T of the field device transistor 10 is normally as high as about 12 to 14 volts. Consequently, to a gate oxide layer of a thickness below 50 .ANG., which normally has a breakdown voltage of about 5 to 6 volts, a conventional field device transistor 10 can no longer provide sufficient protection.
In addition, the thickness of the gate oxide layer 24 of a field device transistor 10 is also directly relates to the threshold voltage V.sub.T of the field device transistor 10. That is, the threshold voltage V.sub.T is increased accordingly to the thickness of the field oxide layer of a field device transistor. Therefore, a field device transistor having a filed oxide layer of about 5000 to 8000 .ANG. is not able to protect the devices of an internal circuit that have field oxide layers below 50 .ANG..